1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to a semiconductor device containing bipolar transistors formed on an insulator such as an insulating substrate, and an insulating film provided on a semiconductor substrate.
2. Description of the Prior Art
Conventional complementary bipolar transistor circuits are shown in FIGS. 3A and 3B. The transistors are employed not only in digital signal applications but also in analog signal application.
In FIGS. 3A and 3B, the reference characters Q1 and Q2 show pnp and npn bipolar transistors, Q3 and 04 show p- and n-channel metal-oxide-semiconductor (MOS) transistors. R shows resistors, and In and Out show input and output ends, respectively. +V.sub.EE and -V.sub.EE shows power source voltages.
with the complementary bipolar transistor circuits as described above, when high-speed operations are necessary, a silicon-on-insulator (SOI) structure has been employed because of less stray capacitance.
FIGS. 1A and 1B show a conventional semiconductor device of SOI structure including high-speed complementary bipolar transistor circuits. FIG. 1A is a plan view of the portion surrounded by a broken line in FIGS. 3A and 3B. FIG. 1B is a cross section along the line IB-IB in FIG. 1A.
As shown in FIG. 1B, a silicon dioxide (SiO.sub.2) film 103 is formed on a silicon substrate 101. First and second island regions I.sub.101 and I.sub.102 are formed on the film 103. The first and second island regions I.sub.101 and I.sub.102 are buried in a silicon nitride (Si.sub.3 N.sub.4) film 109 and a boron-doped phosphosilicate glass (BPSG) film 110 stacked on the silicon dioxide film 103. A silicon dioxide film 113 for masking is formed to cover the first and second island regions I.sub.101 and I.sub.102, the silicon nitride film 109 and the BPSG film 110.
The first and second island regions I.sub.101 and I.sub.102 are produced by patterning an n.sup.- -type silicon substrate provided on the silicon dioxide film 103. The pnp and npn transistors Q1 and Q2 are formed in the first and second island regions I.sub.101 and I.sub.102, respectively.
In the first island region I.sub.101, the pnp transistor Q1 has a p.sup.+ -type collector region 104, an epitaxial region 106a, an n.sup.+ -type base region 111 and a p.sup.+ -type emitter region 114. The base region 111 is electrically connected with a base electrode 117 through a base opening or hole H.sub.51 of the mask dioxide film 113, and the emitter region 114 is electrically connected with an emitter electrode 118 through an emitter opening or hole H.sub.52, of the fill 113.
Similarly, in the second island region I.sub.102, the npn transistor Q2 has an n.sup.+ -type collector region 105, an epitaxial region 106b, a p.sup.+ -type base region 112 and an n.sup.+ -type emitter region 115. The base region 112 is electrically connected with a base electrode 119 through a base opening or hole H.sub.61 of the mask dioxide fill 113, and the emitter region 115 is electrically connected with an emitter electrode 120 through an emitter opening or hole H.sub.62 of the film 113.
The collector regions 104 and 105 of the transistors Q1 and Q2 have pull-up portions 104a and 105a extending to the tops of the island regions I.sub.101 and I.sub.102, respectively. The pull-up portions 104a and 105a are in contact with a common collector electrode 121 through collector openings or holes H.sub.53 and H.sub.63 of the fill 113, respectively. Thus, the collector regions 104 and 105 are electrically connected with the common collector electrode 121.
With the conventional semiconductor device described above, to connect with the collector electrode 121, the p.sup.+ and n.sup.+ -type collector regions 104 and 105 need to be pulled up to the tops of the first and second island regions I.sub.101 and I.sub.102, and then, they need to be contacted with the collector electrode 121 at the tops of the island regions I.sub.101 and I.sub.102. Therefore, there is a limit in reducing device size or chip occupation area, which means that it is difficult to integrate the electronic circuits over the substrate 101 on a larger scale.
In addition, since reduction in contact area between the collector regions 104 and 105 and the collector electrode 121 increases the collector resistances of the transistors Q1 and Q2, impediments or hindrances tend to occur in circuit operation due to large output-level shifting. This leads to less reliability of the semiconductor device.